[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #8 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Wed Jun 24 09:59:28 2015
New Revision: 224890

URL: https://gcc.gnu.org/viewcvs?rev=224890&root=gcc&view=rev
Log:
Fix PR target/66200

This applies the same fix for PR target/66200 for AArch64 on the GCC 5 branch
as on the 4.9 branch. On trunk we've fixed this differently by optimizing
the access to the guard variable using a load acquire style instruction.

2015-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * g++.dg/abi/aarch64_guard1.C: Adjust.

2015-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * configure.host (host_cpu): Add aarch64 case.
        * config/cpu/aarch64/atomic_word.h: New file.



Added:
    branches/gcc-5-branch/libstdc++-v3/config/cpu/aarch64/
    branches/gcc-5-branch/libstdc++-v3/config/cpu/aarch64/atomic_word.h
Modified:
    branches/gcc-5-branch/gcc/config/aarch64/aarch64.c
    branches/gcc-5-branch/gcc/testsuite/ChangeLog
    branches/gcc-5-branch/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
    branches/gcc-5-branch/libstdc++-v3/ChangeLog
    branches/gcc-5-branch/libstdc++-v3/configure.host