[Bug target/64477] [4.9/5 Regression] x86 sse unnecessary GPR spill

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64477

--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #5)
> Uros, your thoughts on this?

All these *r are (were?) necessary for TARGET_INTER_UNIT_MOVES_{TO,FROM}_VEC to
avoid allocating general reg, but to go through memory.

It looks that this particular case is just an oversight, and this alternative
should be defined as (Yi/r/C), as is the case for similar sse2_loadd insn

Otherwise, these constraints were carefully fine-tuned for reload. IRA is
slightly different, and no wonder that these constraints will have to be
re-tuned in coming years.