[Bug target/64661] New: [SH] Allow @(disp,reg) address mode for atomics

[olegendo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64661

            Bug ID: 64661
           Summary: [SH] Allow @(disp,reg) address mode for atomics
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: olegendo at gcc dot gnu.org
            Target: sh*-*-*

Atomics that do not use the 'movli.l' and 'movco.l' insns should be able to use
the '@(disp,reg)' address mode for SImode, since those don't have a R0 operand
restriction.

For example:

void test4 (int* mem)
{
  __atomic_add_fetch (mem + 3, 1, __ATOMIC_ACQ_REL);
}

now compiled with -O2 -m4 -ml -matomic-model=soft-gusa:

        mov     #1,r2
        add     #12,r4

        mova    1f,r0
        mov     r15,r1
        .align 2
        mov     #(0f-1f),r15
0:      mov.l   @r4,r3
        add     r2,r3
        mov.l   r3,@r4
1:      mov     r1,r15

should be:
        mova    1f,r0
        mov     r15,r1
        .align 2
        mov     #(0f-1f),r15
0:      mov.l   @(12,r4),r2   // use @(disp,reg)
        add     #1,r2         // PR 64659
        mov.l   r2,@(12,r4)   // use @(disp,reg)
1:      mov     r1,r15


The 'atomic_<fetchop_name>_fetch<mode>_soft_imask' and
'atomic_nand_fetch<mode>_soft_imask' insns could also use QImode and HImode
@(disp,reg) address modes, since the other operand is already R0.