[Bug target/64477] [4.9/5 Regression] x86 sse unnecessary GPR spill

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64477

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |missed-optimization, ra
           Priority|P3                          |P2

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
We end up with

(note 5 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 5 4 2 (set (mem/c:SI (plus:DI (reg/f:DI 7 sp)
                (const_int -12 [0xfffffffffffffff4])) [1 %sfp+-4 S4 A32])
        (reg:SI 5 di [ a ])) t.c:3 90 {*movsi_internal}
     (nil))
(note 4 2 8 2 NOTE_INSN_FUNCTION_BEG)
(insn 8 4 9 2 (set (reg:V4SI 21 xmm0 [95])
        (vec_merge:V4SI (vec_duplicate:V4SI (mem/c:SI (plus:DI (reg/f:DI 7 sp)
                        (const_int -12 [0xfffffffffffffff4])) [1 %sfp+-4 S4
A32]))
            (const_vector:V4SI [
                    (const_int 0 [0])
                    (const_int 0 [0])
                    (const_int 0 [0])
                    (const_int 0 [0])
                ])
            (const_int 1 [0x1]))) t.c:4 2460 {vec_setv4si_0}
     (nil))

after reload as it seems vec_setv4si_0 doesn't allow a di reg operand?

         Choosing alt 2 in insn 8:  (0) v  (1) C  (2) m {vec_setv4si_0}
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
          alt=0,overall=609,losers=1,rld_nregs=1
          alt=1,overall=0,losers=0,rld_nregs=0
         Choosing alt 1 in insn 2:  (0) m  (1) re {*movsi_internal}
           Spilling non-eliminable hard regs: 7