[Bug target/63949] Aarch64 instruction combiner does not optimize subsi_sxth function as expected (gcc.target/aarch64/extend.c fails)

[vekumar at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63949

--- Comment #7 from vekumar at gcc dot gnu.org ---
I ran GCC tests against the patch found one failure. 

int
adds_shift_ext ( long long a, int b, int c)
{
 long long  d = (a + ((long long)b << 3));

  if (d == 0)
    return a + c;
  else
    return b + d + c;
}


The test expects adds generation and before my fix it is generated .
adds_shift_ext:
        adds    x3, x0, x1, sxtw 3      // 11   *adds_extvdi_multp2     [length
= 4]
        beq     .L5     // 12   *condjump       [length = 4]

But now I am generating sign extends with shifts instead of sign extends with
mul in my patch.

adds_shift_ext:
        add     x3, x0, x1, sxtw 3      // 10   *add_extendsi_shft_di   [length
= 4]
        cbz     x3, .L5 // 12   *cbeqdi1        [length = 4]

We don't have *adds_extendsi_shft_di pattern. We have patterns for
adds_extvdi_multp2 that extends an operation over mult.

Adding one will help optimize this case. But my concern is what if other
targets  hits the same issue?