[Bug target/67325] Optimize shift (aka subreg) of load to simple load

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67325

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|rtl-optimization            |target

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
This is a target issue:
Trying 6 -> 7:
Failed to match this instruction:
(parallel [
        (set (reg:DI 65)
            (sign_extend:DI (mem:SI (plus:DI (reg/v/f:DI 63 [ l ])
                        (const_int 4 [0x4])) [2 *l_1(D)+4 S4 A32])))
        (clobber (reg:CC 17 flags))
    ])
Successfully matched this instruction:
(set (reg:DI 65)
    (sign_extend:DI (mem:SI (plus:DI (reg/v/f:DI 63 [ l ])
                (const_int 4 [0x4])) [2 *l_1(D)+4 S4 A32])))
rejecting combination of insns 6 and 7
original costs 4 + 4 = 8
replacement cost 12
starting the processing of deferred insns
ending the processing of deferred insns

So GCC is able to do it but rejects it because the cost is worse for some
reason.

That is it is replacing:
(insn 6 3 7 2 (set (reg:DI 66 [ *l_1(D) ])
        (mem:DI (reg/v/f:DI 63 [ l ]) [2 *l_1(D)+0 S8 A64])) t1.c:2 62
{*movdi_internal_rex64}
     (expr_list:REG_DEAD (reg/v/f:DI 63 [ l ])
        (nil)))

(insn 7 6 13 2 (parallel [
            (set (reg:DI 65)
                (ashiftrt:DI (reg:DI 66 [ *l_1(D) ])
                    (const_int 32 [0x20])))
            (clobber (reg:CC 17 flags))
        ]) t1.c:2 530 {*ashrdi3_1}
     (expr_list:REG_DEAD (reg:DI 66 [ *l_1(D) ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))

With the above.  Note the clobber gets in the way of combining with the next
insn of the subreg.