[Bug target/65697] __atomic memory barriers not strong enough for __sync builtins

mwahab at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Wed Apr 15 14:33:00 GMT 2015


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65697

--- Comment #19 from mwahab at gcc dot gnu.org ---
(In reply to Andrew Haley from comment #18)
> (In reply to mwahab from comment #17)
> 
> > ----
> > int cas(int* barf, int* expected, int* desired)
> > {
> >   return __atomic_compare_exchange_n(barf, expected, desired, 0,
> > 				     __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
> > }
> > ----
> > cas:
> > 	ldr	w3, [x1]
> > .L3:
> > 	ldaxr	w4, [x0]
> > 	cmp	w4, w3
> > 	bne	.L4
> > 	stlxr	w5, w2, [x0]  ; store-release
> > 	cbnz	w5, .L3
> > .L4:
> > 	cset	w0, eq
> > 	cbz	w0, .L6
> > 	ret
> > 	.p2align 3
> > .L6:
> > 	str	w4, [x1]  ; store, no barrier.
> > 	ret
> > ----
> > 
> > This looks odd to me but I'd need look into it more.
> 
> That looks fine to me: if the CAS fails, the prev value -> *expected.

It looks inconsistent with C11 S7.17.7.4-2 (C++11 S29.6.4-21) "Further, if the
comparison is true, memory is affected according to the value of success, and
if the comparison is false, memory is affected according to the value of
failure." (where success and failure are the memory model arguments.) In this
case, the write to *exp should be memory_order_seq_cst.


More information about the Gcc-bugs mailing list