[Bug target/65697] __atomic memory barriers not strong enough for __sync builtins

aph at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Wed Apr 15 10:16:00 GMT 2015


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65697

Andrew Haley <aph at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |aph at gcc dot gnu.org

--- Comment #13 from Andrew Haley <aph at gcc dot gnu.org> ---
There's surely a documentation problem here.

GCC defines this:

`__ATOMIC_SEQ_CST'
     Full barrier in both directions and synchronizes with acquire
     loads and release stores in all threads.

But LDAXR/STLXR doesn't do that, and there's no write barrier at all when the
compare fails.  If the intention really is to map onto c++11, this
specification is wrong.

But if this specification is correct, then

bool gcc_cas() {
  int expected = 1;
  int desired = 2;
  return __atomic_compare_exchange(&barf, &expected, &desired, false,
                                   __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
}

gcc_cas():
    sub    sp, sp, #16
    mov    w1, 1
    adrp    x0, .LANCHOR0
    str    w1, [sp,12]
    add    x0, x0, :lo12:.LANCHOR0
    mov    w2, 2
.L10:
    ldaxr    w3, [x0]
    cmp    w3, w1
    bne    .L11
    stlxr    w4, w2, [x0]
    cbnz    w4, .L10
.L11:
    cset    w0, eq
    add    sp, sp, 16
    ret

is wrong.



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