[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

vmakarov at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Thu Apr 9 19:40:00 GMT 2015


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #3 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
Author: vmakarov
Date: Thu Apr  9 19:40:09 2015
New Revision: 221956

URL: https://gcc.gnu.org/viewcvs?rev=221956&root=gcc&view=rev
Log:
2015-04-09  Vladimir Makarov  <vmakarov@redhat.com>

    PR target/65710
    * lra-int.h (lra_bad_spill_regno_start): New.
    * lra.c (lra_bad_spill_regno_start): New.
    (lra): Set up lra_bad_spill_regno_start.  Set up
    lra_constraint_new_regno_start unconditionally.
    * lra-assigns.c (spill_for): Use lra_bad_spill_regno_start for
    spill preferences.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/lra-assigns.c
    trunk/gcc/lra-int.h
    trunk/gcc/lra.c



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