[Bug target/53513] [SH] Add support for fschg and fpchg insns and improve fenv support

[olegendo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53513

Oleg Endo <olegendo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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  Attachment #33717|0                           |1
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--- Comment #27 from Oleg Endo <olegendo at gcc dot gnu.org> ---
Created attachment 33721
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33721&action=edit
Using virtual FPSCR registers to model insn dependencies

Updated patch that avoids the single_set problems by using (clobber (reg:SI
FPSCR_STAT_REG)) instead of a set.  This also eliminates the fsca pattern
changes in the previous patch.  Since the 'fpu_switch' insn is still a multiple
set insn, it won't be used for delay slot stuffing, but this is a minor issue
that can be addressed later.  I'm testing the patch now on sh-sim.  At least
'make all' works.