[Bug target/58139] PowerPC volatile VSX register live across call

[macro@linux-mips.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58139

--- Comment #15 from Maciej W. Rozycki <macro@linux-mips.org> ---
There is no ICE, this is target code in libgcc_s.so.1 calling abort at
run time whenever the DWARF2 unwinder is called.  Shall I send you
binaries?

NB SPE GPRs indeed are 64-bit wide even on 32-bit targets with the extra
32 bits only used for SPE data types, traditionally V2SI mode integers.
This makes a change in the ABI though such that any GPRs stored in stack
frames are held there as 64-bit quantities, with `evstdd' and `evldd'
intructions used to manipulate them.  For regular, non-vector integer
operations GPRs remain 32-bit, with the most significant 32 bits unused.

So this may or may not be a latent bug for SPE that, if so, I'd love to
see fixed in trunk, however speaking of 4.8 this is a serious regression
as the DWARF2 unwinder used to work and now it does not, making exception
handling non-functional.

Of course if you are able to fix 4.8 properly right away, then it would
be most welcome!