[Bug rtl-optimization/54300] [4.7 Regression] Erroneous optimization causes wrong Neon data management
rearnsha at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Fri Oct 4 17:29:00 GMT 2013
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54300
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Component|target |rtl-optimization
Known to fail| |4.9.0
--- Comment #9 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
This is regcprop messing up. After the ce3 pass we have:
(insn 18 30 73 4 (set (reg:V4HI 54 d19 [orig:113 D.16370 ] [113])
(unspec:V4HI [
(mem:V4HI (reg:SI 14 lr [128]) [0 MEM[(const
__builtin_neon_hi[4] *)_21]+0 S8 A16])
] UNSPEC_VLD1))
/work/rearnsha/scratch/gnu/gcc/trunk/gcc/include/arm_neon.h:8019 1662
{neon_vld1v4hi}
(nil))
(insn 73 18 27 4 (parallel [
(set (reg:V4HI 52 d18 [ D.16372 ])
(reg:V4HI 54 d19 [orig:113 D.16370 ] [113]))
(set (reg:V4HI 54 d19 [ D.16372+8 ])
(reg:V4HI 52 d18 [orig:120 D.16370 ] [120]))
]) /work/rearnsha/scratch/gnu/gcc/trunk/gcc/include/arm_neon.h:5783
1429 {*neon_vswpv4hi}
(expr_list:REG_UNUSED (reg:V4HI 54 d19 [ D.16372+8 ])
(nil)))
(insn 27 73 31 4 (set (reg:V4SI 52 d18 [orig:118 D.16373 ] [118])
(unspec:V4SI [
(reg:V4HI 52 d18 [orig:115 D.16372 ] [115])
(const_int 1 [0x1])
] UNSPEC_VMOVL))
/work/rearnsha/scratch/gnu/gcc/trunk/gcc/include/arm_neon.h:6183 1470
{neon_vmovlv4hi}
(nil))
and regcprop substitues d19 for d18 in insn 27, missing the fact that insn 73
is swapping the two values (thus clobbering the old d19 value). Giving:
(insn 27 73 31 4 (set (reg:V4SI 52 d18 [orig:118 D.16373 ] [118])
(unspec:V4SI [
(reg:V4HI 54 d19 [orig:115 D.16372 ] [115])
(const_int 1 [0x1])
] UNSPEC_VMOVL))
/work/rearnsha/scratch/gnu/gcc/trunk/gcc/include/arm_neon.h:6183 1470
{neon_vmovlv4hi}
(nil))
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