[Bug target/57744] New: Power8 support has problems with quad word atomic instructions

[meissner at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57744

            Bug ID: 57744
           Summary: Power8 support has problems with quad word atomic
                    instructions
           Product: gcc
           Version: 4.9.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org

The lqarx and stqcx. instructions will sometimes generate code using an
odd/even register combination.  The assembler complains about this, since only
even/odd registers can be used.

This is due to the atomic support for quad using PTImode to force allocation of
an even/odd register pair.  However, since MODES_TIEABLE_P(PTImode, TImode)
returns 1, the compiler felt it could tie together the value originally in a
TImode register with the PTImode register, and an odd/even TImode had already
been allocated.

In looking at MODES_TIEABLE_P, I feel that small integer modes (QImode, HImode,
SImode) should not be tied with larger modes like DImode, since DImode can go
in floating point registers, but SImode can't.