[Bug target/57648] New: Illegal use ARM Cortex M3 instruction LDMIA causes UserFault

v.van.beveren at nikhef dot nl gcc-bugzilla@gcc.gnu.org
Wed Jun 19 07:52:00 GMT 2013


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57648

            Bug ID: 57648
           Summary: Illegal use ARM Cortex M3 instruction LDMIA causes
                    UserFault
           Product: gcc
           Version: 4.7.2
            Status: UNCONFIRMED
          Severity: major
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: v.van.beveren at nikhef dot nl

Created attachment 30322
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=30322&action=edit
Test-case generating UserFault

When copying a struct into another struct, GCC's ARM back-end generates code in
which the LDMIA instruction is used. This instruction expects word-aligned
addresses. However, in some cases this is not true, causing a UserFault.

See this function:

  TestStruct target;

  void copyStruct(TestStruct * toCopy)
  {
    target = *toCopy;   // illegal instruction is generated here.
  }

Causes this code to be generated:

000005d8 <copyStruct>:
     5d8:    b082          sub    sp, #8
     5da:    9001          str    r0, [sp, #4]
     5dc:    4b03          ldr    r3, [pc, #12]    ; (5ec <copyStruct+0x14>)
     5de:    9a01          ldr    r2, [sp, #4]
     5e0:    ca07          ldmia    r2, {r0, r1, r2} ; UserFault if (r2 & 0x3)
!= 0
     5e2:    e883 0007     stmia.w    r3, {r0, r1, r2}
     5e6:    b002          add    sp, #8
     5e8:    4770          bx    lr
     5ea:    bf00          nop
     5ec:    200005ec     .word    0x200005ec

Its not said in so-many words in the ARM description, but I believe that r2 at
line 0x5e0 should be word aligned. I have verified with a debugger that this is
the line which causes the UserFault.

See:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABCAEDD.html

Complete test-case attached. Note that I used an Energy Micro Cortex M3
processor. You may need to modify it for your specific MCU. In this scenario it
does not matter what optimization one enables, however, I first noticed the
issue when compiling with -Os, which caused packing and non-word aligned
structures.



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