[Bug tree-optimization/56035] [4.8 Regression] ICE in verify_loop_structure, at cfgloop.c:1581 (=?UTF-8?Q?loop=20n=E2=80=99s=20header=20does=20not=20belong=20directly=20to=20it=20=21?=)

[mpolacek at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56035

--- Comment #4 from Marek Polacek <mpolacek at gcc dot gnu.org> 2013-01-22 10:22:21 UTC ---
The problem looks to be in fix_loop_structures:
      /* If there was no latch, schedule the loop for removal.  */
      if (!first_latch)
        loop->header = NULL;
      /* If there was a single latch and it belongs to the loop of the
         header, record it.  */
      else if (latch
               && latch->src->loop_father == loop)
        loop->latch = latch->src;
      /* Otherwise there are multiple latches which are eventually
         disambiguated below.  */
      else 
        loop->latch = NULL;
we have the first_latch and there's only one latch edge, so we should the the
else if branch.  But we don't, since latch->src->loop_father != loop.  It looks
like the loop_father info isn't correct at all, ->loop_father->num is always 0,
but if we defer re-computing the latches to after re-scanning the bodies of
loops and fixing the nesting, everything seems to be fine (and the final
assembly is the same as before r194582).

The CFG is quite weird though, e.g. EXIT has no predecessors at all.