[Bug target/59539] Missed optimisation: VEX-prefixed operations don't need aligned data

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59539

--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #4)
> > From a quick look at the patch, the proposed patch doesn't support masked
> > insns. 
> > 
> > I think it is better to introduce corresponding sse.md expanders for
> > UNSPEC_STOREU and UNSPEC_LOADU insns. These expanders will either generate
> > UNSPEC_* pattern or "normal" (masked) move in case of TARGET_AVX.
> 
> I can surely add the expanders, but don't understand the comment about
> masked moves.  *maskload* is already a specialized UNSPEC, and can't really
> be merged with arithmetic patterns (ok, perhaps with -mavx512f?) and handles
> both aligned and unaligned operands the same.

Ah, sorry for being terse, I was looking at avx512f_storeu_..._mask. I assume
that this pattern can be combined as a memory operand into other SSE
instructions, in the same way as non-masked UNSPEC_* patterns. Admittedly, we
are in the middle of avx512f merge, so this assumption may be wrong.