[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #5)
> (In reply to Uroš Bizjak from comment #4)
> > (In reply to Jakub Jelinek from comment #3)
> > > Likely caused by r198611.
> > 
> > This is the patch that exposes the problem.
> > 
> > I have filled this PR due to the difference with IRA vs. reload, it looks
> > that spill size should be somehow taken into account.
> 
> What was the point of the r198611 patch other than macroizing some insns
> though?
> Isn't it worth to just restore the previous behavior when it worked properly
> with both reload and LRA?

The patch added missing alternative (xmm->mem, IIRC) that exposed this problem.
Since there is no other weight in play, IRA is now free to spill V4SI input
value from xmm register and later parially load SImode to an integer register.
However, we have better alternative at hand, where we can spill SImode value.

Many other examples can be constructed for -march=k8, where interunit moves are
disabled. -march=core2 and other intel processors are immune to this problem.

This is the reason why I think this problem should be solved in IRA in a
generic way. IRA should choose the most appropriate register spill out of
otherwise equal choices based on some criteria, so we won't have to
artificially limit insn alternatives.