[Bug target/54682] New: [SH] Replace constant loads with reg-reg copies

[olegendo at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54682

             Bug #: 54682
           Summary: [SH] Replace constant loads with reg-reg copies
    Classification: Unclassified
           Product: gcc
           Version: 4.8.0
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: olegendo@gcc.gnu.org
            Target: sh*-*-*


I've noticed that quite often code such as this is generated:

  mov   #15,r4
  mov   r0,r8
  mov   #0,r5
  mov   #0,r6
  jsr   @r10
  mov   #0,r7

On SH4A the insn 'mov #imm,Rn' is a MT group insn and can be executed in
parallel. On SH4 this is an EX group insn and can't be executed in parallel.
Moreover on SH4 and SH2A the insn 'mov Rm,Rn' is a zero-latency insn and can be
executed in parallel with any other insn.  Thus the above sequence should be
something like:

  mov   #15,r4
  mov   r0,r8
  mov   #0,r5
  mov   r5,r6
  jsr   @r10
  mov   r5,r7

As far as I know these constant loads might also be generated during reload. 
Peepholes probably won't catch all opportunities, since constant loads can be
disjunct.  Probably this could be done by split patterns after reload, which
look for preceding constant loads and split into reg-reg moves.