[Bug target/44141] Redundant loads and stores generated for AMD bdver1 target

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44141

--- Comment #20 from uros at gcc dot gnu.org 2012-05-09 18:06:52 UTC ---
Author: uros
Date: Wed May  9 18:06:47 2012
New Revision: 187347

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=187347
Log:
    PR target/44141
    * config/i386/i386.c (ix86_expand_vector_move_misalign): Do not handle
    128 bit vectors specially for TARGET_AVX.  Emit sse2_movupd and
    sse_movupd RTXes for TARGET_AVX, TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
    or when optimizing for size.
    * config/i386/sse.md (*mov<mode>_internal): Remove
    TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling from asm output code.
    Calculate "mode" attribute according to optimize_function_for_size_p
    and TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL flag.
    (*<sse>_movu<ssemodesuffix><avxsizesuffix>): Choose asm template
    depending on the mode of the instruction.  Calculate "mode" attribute
    according to optimize_function_for_size_p, TARGET_SSE_TYPELESS_STORES
    and TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL flags.
    (*<sse2>_movdqu<avxsizesuffix>): Ditto.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c
    trunk/gcc/config/i386/sse.md