[Bug target/44141] Redundant loads and stores generated for AMD bdver1 target

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44141

--- Comment #18 from Uros Bizjak <ubizjak at gmail dot com> 2012-05-08 10:32:33 UTC ---
(In reply to comment #17)
> Which makes this a target bug then.  Uros?

Following the explanation in comment #16, I'd say so.

Please note that we already implement the radical change, mentioned at the end
of the comment, but for TARGET_AVX only (please see *mov<mode>_internal
patterns in config/i386/sse.md), and the less radical change with
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL in move patterns. As suggested, we will
add T_S_P_S_I_O handling in movu patterns, avoiding mode changes entirely.

Also, it looks that vector move patterns need some TLC.