[Bug middle-end/53623] [4.7/4.8 Regression] sign extension is effectively split into two x86-64 instructions

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53623

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |jakub at gcc dot gnu.org

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-06-11 12:20:45 UTC ---
This is different from PR50176, at least the incomplete patch there wouldn't do
anything for this testcase (the PR50176 problem is QImode and 32-bit IA-32 code
with the unavailability of %sil/%dil/%bpl registers).
The problem in this PR (at least that we don't generate the same code as 4.6
did) is that the REE pass doesn't do anything here, because of the
  && REGNO (dest) == REGNO (XEXP (src, 0))
check in add_removable_extension.  We have
  (set (reg:HI %ax) (mem:HI (whatever)))
  (set (reg:DI %rdx) (sign_extend:DI (reg:HI %ax))
  (set (reg:DI %rax) (zero_extend:DI (reg:QI %al))
and when processing the sign_extend, we give up because of that failed REGNO ==
REGNO check, and while we queue the zero_extend, that alone can't be optimized,
both as it is a MEM:HI load, not QImode load, and because changing it into
movzbl would make the sign extension wrong.

Perhaps we could extend the REE pass for this slightly, by allowing REGNO !=
REGNO, if there is just a single reaching def and the REGNO != REGNO extension
is the first use of that reg (i.e. all other uses are dominated by the
extension being considered).  Then perhaps we could attempt to change the load
from loading into reg:HI %ax into sign extending load from HI to reg:DI %rdx,
followed by either adding there a (set (reg:DI %rax) (reg:DI %rdx)) move where
the sign extension currently is (and hoping some further pass will propagate
that into all other uses), or changing all uses (from ax/al to dx/dl) right
away.