[Bug rtl-optimization/46843] ICE: in spill_failure, at reload1.c:2157 -fschedule-insns -fsched-pressure

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46843

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2012-07-13
   Target Milestone|---                         |4.6.4
            Summary|ICE: in spill_failure, at   |ICE: in spill_failure, at
                   |reload1.c:2157              |reload1.c:2157
                   |-fschedule-insns            |-fschedule-insns
                   |-fsched-pressure when using |-fsched-pressure
                   |doubles                     |
     Ever Confirmed|0                           |1
      Known to fail|                            |4.7.2, 4.8.0

--- Comment #1 from Uros Bizjak <ubizjak at gmail dot com> 2012-07-13 15:07:28 UTC ---
Confirmed.

sched1 pass is moving insn that reads CX hard register after the shift:

(insn 20 7 10 2 (parallel [
            (set (reg/v:SI 64 [ n ])
                (ashift:SI (reg:SI 85)
                    (reg:QI 37 r8 [ s ])))
            (clobber (reg:CC 17 flags))
        ]) pr46843.c:3 498 {*ashlsi3_1}
     (expr_list:REG_DEAD (reg:SI 85)
        (expr_list:REG_DEAD (reg:QI 37 r8 [ s ])
            (expr_list:REG_UNUSED (reg:CC 17 flags)
                (nil)))))

(insn 10 20 13 2 (set (reg/v/f:DI 81 [ d2 ])
        (reg:DI 2 cx [ d2 ])) pr46843.c:2 63 {*movdi_internal_rex64}
     (expr_list:REG_DEAD (reg:DI 2 cx [ d2 ])
        (nil)))

Probably not a good idea to increase live ranges of hard registers before
register allocation pass.

This PR is somehow related to PR 53942, where combine pass increased live range
of CX register after shift insn.