[Bug target/51821] [4.5/4.6/4.7 Regression] 64bit > 32bit conversion produces incorrect results with optimizations
ubizjak at gmail dot com
gcc-bugzilla@gcc.gnu.org
Wed Jan 11 13:13:00 GMT 2012
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51821
--- Comment #4 from Uros Bizjak <ubizjak at gmail dot com> 2012-01-11 13:12:48 UTC ---
In fact, peephole2 pass fails to allocate correct scratch.
We have:
(insn 7 19 16 2 (parallel [
(set (reg:DI 0 ax [65])
(ashift:DI (const_int -1 [0xffffffffffffffff])
(reg:QI 2 cx [orig:63 shift_size ] [63])))
(clobber (reg:CC 17 flags))
]) pr51821.c:8 489 {*ashldi3_doubleword}
(expr_list:REG_DEAD (reg:QI 2 cx [orig:63 shift_size ] [63])
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_UNUSED (reg:SI 1 dx)
(expr_list:REG_EQUAL (ashift:DI (const_int -1
[0xffffffffffffffff])
(subreg:QI (reg/v:SI 2 cx [orig:63 shift_size ] [63])
0))
(nil))))))
With following peephole2 pattern:
(define_peephole2
[(match_scratch:DWIH 3 "r")
(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
(ashift:<DWI>
(match_operand:<DWI> 1 "nonmemory_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_dup 3)]
"TARGET_CMOVE"
[(const_int 0)]
"ix86_split_ashl (operands, operands[3], <DWI>mode); DONE;")
(operand 3) gets SImode dx register that clobers internal processing:
(insn 28 27 29 2 (parallel [
(set (reg:SI 1 dx)
(const_int 0 [0]))
(clobber (reg:CC 17 flags))
]) pr51821.c:8 -1
(nil))
(insn 29 28 30 2 (set (reg:CCZ 17 flags)
(compare:CCZ (and:QI (reg:QI 2 cx [orig:63 shift_size ] [63])
(const_int 32 [0x20]))
(const_int 0 [0]))) pr51821.c:8 -1
(nil))
(insn 30 29 31 2 (set (reg:SI 1 dx [+4 ])
(if_then_else:SI (ne (reg:CCZ 17 flags)
(const_int 0 [0]))
(reg:SI 0 ax [65])
(reg:SI 1 dx [+4 ]))) pr51821.c:8 -1
(nil))
(insn 31 30 16 2 (set (reg:SI 0 ax [65])
(if_then_else:SI (ne (reg:CCZ 17 flags)
(const_int 0 [0]))
(reg:SI 1 dx)
(reg:SI 0 ax [65]))) pr51821.c:8 -1
(nil))
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