[Bug target/53124] Arm NEON narrowing right shift instructions impose incorrect operand bounds (intrinsic and asm)

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53124

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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             Status|UNCONFIRMED                 |RESOLVED
         Resolution|                            |FIXED

--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> 2012-04-26 16:47:38 UTC ---
(In reply to comment #3)
> (In reply to comment #2)
> > The compiler and assembler are correct.  The instruction is:
> > 
> > VSHRN.I<size> Dd, Qm, #imm 
> > 
> > and the immediate, imm, must be in the range 1..size/2
> > 
> > So for vshrn.i32 imm must be in the range 1..16
> > 
> I apologize if I miss something but,as far as I can see, the ARM docs clearly
> say the imm should be in 0..size-1 range (see the link to the above). This is
> the nature of the bug.
> 

What ARM docs?  The ARM ARM (which is the doc that counts) is as I've stated.