[Bug target/53110] GCC-4.7 generates stupid x86_64 asm

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53110

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-04-25 13:02:26 UTC ---
Created attachment 27235
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=27235
gcc48-pr53110.patch

Totally untested patch.  We already have a splitter to handle and by
0xffffffff,
0xffff and 0xff, but it only triggers if the register is different and IMHO it
is quite late anyway.  This attempts to optimize this already during expansion,
perhaps giving the register allocator more freedom (unfortunately it doesn't
seem to improve the code in this case and the movl %edi, %edi (and for %esi
too) stays.  Ideally if RA swapped the two, it could movl %edi, %r8d and shrl
$32, %rdi instead of movq %rdi, %r8; shrl $32, %r8; movl %edi, %edi).