[Bug target/48673] [4.7 Regression] GCC generates WAW and RAW conflicts on IA64.

[abel at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48673

--- Comment #7 from Andrey Belevantsev <abel at gcc dot gnu.org> 2011-05-06 12:33:39 UTC ---
(In reply to comment #6)
> (In reply to comment #5)
> > Or schedule_block could have a mode of preserving the existing insn order,
> > which can also be useful for testing purposes.  If this sounds like an
> > overkill, something like sel-sched.c:reset_sched_cycles_in_current_ebb could be
> > adapted to work.  This function feeds the bb insns to DFA but also follows the
> > old schedule w.r.t. to dependency latencies.  Not having the old schedule would
> > mean that we would honor only DFA latencies reflected in insn cycles and
> > TImodes, but this may be enough.
> 
> That sounds fragile. The DFA is not sufficient to produce an accurate schedule
> on all targets. If SMS produces a schedule it might as well mark it with
> accurate uses of TImode.

But sms works too early.  There is no guarantee that TImode markers will live
until machreorg, where we need them.  Also, for the before reload scheduler
there is no guarantee the schedule would be fully accurate.

If you are saying that just DFA is not enough for making proper TImodes, then
IMHO the only choice is to have the full run of schedule_block preserving insn
order and taking into account all of DFA/dependency/target hook stuff just
before the machreorg pass.