[Bug tree-optimization/37916] [4.3/4.4/4.5/4.6 Regression] SSA names causing register pressure; unnecessarily many simultaneously "live" names.

[hp at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37916

--- Comment #20 from Hans-Peter Nilsson <hp at gcc dot gnu.org> 2011-03-11 01:31:14 UTC ---
(In reply to comment #19)
> Random thought on this PR: With a scheduler description, -fschedule-insns
> -fsched-pressure may help.

That theory should be testable by compiling for e.g. a x86_64 target; see
comment #12, but to answer your question...

> Is there a reason why there is no scheduler description?

Yes.  For a while, there was nothing to schedule.

...except for CPUs in systems a cache, where it helps to schedule to avoid RaW
hazards.
...and then pipelined variants came, with other hazards to schedule (to avoid
bubbles, no mips1-type madness).
...but then, I noticed that scheduling with the "new" scheduler wasn't
supported for CC0 targets.
...which later was either fixed, or just a plain misunderstanding (cf.
m68k/cf.md).
...and when checking the cycle-correct simulator, I found that there weren't
many cycles to schedule away, hence a fair amount of work for no apparent gain,
at least for the intended purpose of insn scheduling.

There you go, the reasons in a nutshell.  And while there's still a possibility
that it's a pragmatic solution (modulo #c12), it doesn't strike me as requiring
a scheduler to be the Right Thing to do for a fix to this problem.
(Though from a general GCC maintenance perspective, automatically defaulting to
a trivial scheduler might be a good idea.)