[Bug target/49263] SH Target: underutilized "TST #imm, R0" instruction

[oleg.endo@t-online.de]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49263

--- Comment #1 from Oleg Endo <oleg.endo@t-online.de> 2011-06-01 20:42:00 UTC ---
Created attachment 24412
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=24412
Proposed Patch

Although the patch gets the job done, programmer's sense tells me it is fishy,
or at least pretty much brute forced cure of the symptoms, not the cause. It's
my first GCC patch, so any feedback is highly appreciated.

What I did was looking at the RTL, in particular the combine pass, identifying
patterns it failed to find a "shortcut" (tst insn) for and adding them to the
insn descriptions. 

I also had to expand the costs calculation of the AND instruction to cover AND,
OR and XOR (on SH they are the same anyways), or else the cost of a matched
replacement insn would result in a rejection in the combine pass.