[Bug rtl-optimization/51069] [4.7 Regression] ICE in verify_loop_structure, at cfgloop.c:1559

[hubicka at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51069

--- Comment #6 from Jan Hubicka <hubicka at gcc dot gnu.org> 2011-12-27 18:50:14 UTC ---
OK,
the problem is that by removing conditional entrance into irreducible region,
the BB becomes part of the region itself.
I am testing the following patch
Index: cfgloopmanip.c
===================================================================
--- cfgloopmanip.c      (revision 182692)
+++ cfgloopmanip.c      (working copy)
@@ -290,6 +290,7 @@ remove_path (edge e)
   int i, nrem, n_bord_bbs;
   sbitmap seen;
   bool irred_invalidated = false;
+  edge_iterator ei;

   if (!can_remove_branch_p (e))
     return false;
@@ -329,9 +330,12 @@ remove_path (edge e)
   /* Find "border" hexes -- i.e. those with predecessor in removed path.  */
   for (i = 0; i < nrem; i++)
     SET_BIT (seen, rem_bbs[i]->index);
+  FOR_EACH_EDGE (ae, ei, e->src->succs)
+    if (ae != e && ae->dest != EXIT_BLOCK_PTR && !TEST_BIT (seen,
ae->dest->index)
+       && ae->flags & EDGE_IRREDUCIBLE_LOOP)
+      irred_invalidated = true;
   for (i = 0; i < nrem; i++)
     {
-      edge_iterator ei;
       bb = rem_bbs[i];
       FOR_EACH_EDGE (ae, ei, rem_bbs[i]->succs)
        if (ae->dest != EXIT_BLOCK_PTR && !TEST_BIT (seen, ae->dest->index))