[Bug bootstrap/45445] [4.6 regression] ARM bootstrap failure: comparison failures after stage 3
mikpe at it dot uu dot se
gcc-bugzilla@gcc.gnu.org
Wed Sep 8 12:24:00 GMT 2010
------- Comment #6 from mikpe at it dot uu dot se 2010-09-08 12:24 -------
The smallest .o file that differs between stage2 and stage3 is sreal.o. Diffing
the objdump -d output shows:
@@ -1,5 +1,5 @@
-stage2-gcc/sreal.o: file format elf32-littlearm
+stage3-gcc/sreal.o: file format elf32-littlearm
Disassembly of section .text:
@@ -19,7 +19,7 @@
2c: 01520004 cmpeq r2, r4
30: 3a000011 bcc 7c <normalize.isra.1+0x7c>
34: e5911000 ldr r1, [r1]
- 38: e0944004 adds r4, r4, r4
+ 38: e1b04084 lsls r4, r4, #1
3c: e0a55005 adc r5, r5, r5
40: e1530005 cmp r3, r5
44: 01520004 cmpeq r2, r4
That is, a single adds became an lsls instead.
cfgloopanal.o and tree-ssa-loop-ivcanon.o show the exact same one-instruction
adds-became-lsls difference.
double-int.o has more elaborate differences:
@@ -1,5 +1,5 @@
-stage2-gcc/double-int.o: file format elf32-littlearm
+stage3-gcc/double-int.o: file format elf32-littlearm
Disassembly of section .text:
@@ -427,13 +427,13 @@
674: e1a0c33c lsr ip, ip, r3
678: e58d4018 str r4, [sp, #24]
67c: e58d2020 str r2, [sp, #32]
- 680: e1cd21d8 ldrd r2, [sp, #24]
- 684: e0922002 adds r2, r2, r2
- 688: e58d5024 str r5, [sp, #36] ; 0x24
+ 680: e58d5024 str r5, [sp, #36] ; 0x24
+ 684: e1cd21d8 ldrd r2, [sp, #24]
+ 688: e1b02082 lsls r2, r2, #1
68c: e0a33003 adc r3, r3, r3
- 690: e1cd02d0 ldrd r0, [sp, #32]
- 694: e1822000 orr r2, r2, r0
- 698: e1833001 orr r3, r3, r1
+ 690: e1cd42d0 ldrd r4, [sp, #32]
+ 694: e1822004 orr r2, r2, r4
+ 698: e1833005 orr r3, r3, r5
69c: e58ab000 str fp, [sl]
6a0: e58ac004 str ip, [sl, #4]
6a4: e1c820f0 strd r2, [r8]
I'll try to extract a test case from one of these.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45445
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