[Bug rtl-optimization/46514] 128-bit shifts on x86_64 generate silly code unless the shift amount is constant

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46514

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
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             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2010.11.17 19:51:24
     Ever Confirmed|0                           |1

--- Comment #1 from Uros Bizjak <ubizjak at gmail dot com> 2010-11-17 19:51:24 UTC ---
This is how doubleword (TImode on x86_64 and DImode on x86_32 targets) shifts
are handled. Doubleword instructions are expanded to final instruction sequence
late after register allocation pass, so earlier optimization passes know that
they are processing SHIFT expressions and optimize them as shifts.

The expansion detects constant count operand and emits special sequence, but
for sure it can't detect limited set of possible count operands, and emits
universal sequence in this case.

That said, doubleword operation code is not the most optimized code around, on
the grounds that it is usually not used in performance critical part of the
application. Just try to avoid it as much as possible.