[Bug target/46883] GCC ICE with error: unrecognizable insn

[uweigand at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46883

Ulrich Weigand <uweigand at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |bernds at codesourcery dot
                   |                            |com, uweigand at gcc dot
                   |                            |gnu.org

--- Comment #3 from Ulrich Weigand <uweigand at gcc dot gnu.org> 2010-12-13 18:54:48 UTC ---
Confirmed.  A somewhat shorter testcase is:

void
bar (unsigned char *q, unsigned short *data16s, int len)
{
  int i;

  for (i = 0; i < len; i++)
    {
      q[2 * i] =
        (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF)) & 0xFF;
      q[2 * i + 1] =
        ((unsigned short)
         (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF))) >> 8;
    }
}

The problem seems to be that an insn:
(insn 88 86 90 4 (set (reg:SI 240)
        (zero_extend:SI (subreg:QI (mem:HI (post_inc:SI (reg:SI 220 [ ivtmp.22
])) [2 MEM[(short unsigned int *)D.2066_62 + 4294967294B]+0 S2 A16]) 0)))
a.c:10 152 {*arm_zero_extendqisi2}
     (expr_list:REG_INC (reg:SI 220 [ ivtmp.22 ])
        (nil)))

gets transformed by a splitter into:
(insn 122 86 90 4 (set (reg:SI 240)
        (and:SI (subreg:SI (mem:HI (post_inc:SI (reg:SI 220 [ ivtmp.22 ])) [2
MEM[(short unsigned int *)D.2066_62 + 4294967294B]+0 S2 A16]) 0)
            (const_int 255 [0xff]))) a.c:10 -1
     (expr_list:REG_INC (reg:SI 220 [ ivtmp.22 ])
        (nil)))

But this isn't accepted by the andsi3 pattern, since the (subreg (mem ..)) does
not match the s_register_operand predicate.

The splitter
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
  "!arm_arch6"
  [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
{
  operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
  if (TARGET_ARM)
    {
      emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255)));
      DONE;
    }
})

was introduced by Bernd Schmidt's patch to improve zero- and sign-extension
handling on ARM (committed 2010-07-02), PR 42172:
http://gcc.gnu.org/ml/gcc-patches/2010-06/msg00832.html

Bernd, do you have any suggestions how to fix this?