[Bug target/40835] redundant comparison instruction
steven at gcc dot gnu dot org
Fri Jul 24 07:00:00 GMT 2009
------- Comment #3 from steven at gcc dot gnu dot org 2009-07-24 06:59 -------
Because HAVE_cc0 is only for cc0 targets, and ARM is not one of those?
You should stop jumping to peepholes for every missed optimization you find.
There is a csecc pass (part of cse2) that should handle this. You should try to
figure out why that pass can't optimize away your redundant insn.
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