[Bug target/40487] Extra zero extensions produced for ARM.

[rearnsha at gcc dot gnu dot org]

------- Comment #11 from rearnsha at gcc dot gnu dot org  2009-07-14 14:53 -------
The following define_split works for this specific case, but it needs to be
made more generic (handling IOR and HImode variants).

It also needs reworking for big-endian -- that needs (subreg...3).

(define_split
  [(set (match_operand:SI 0 "s_register_operand" "")
        (xor:SI (and:SI (ashift:SI (match_operand:SI 1 "s_register_operand" "")
                                   (match_operand:SI 2 "const_int_operand" ""))
                        (match_operand:SI 3 "const_int_operand" ""))
                (zero_extend:SI (subreg:QI (match_dup 1) 0))))]
  "TARGET_32BIT && INTVAL (operands[3]) == (255 & (255 << (INTVAL
(operands[2]))))"
  [(set (match_dup 0) (xor:SI (ashift:SI (match_dup 1) (match_dup 2))
                              (match_dup 1)))
   (set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))]
  "")


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40487