[Bug target/38931] [4.4 Regression] Seg fault when getting instruction latency on a *movsi_1 with an MMX target register

[pinskia at gcc dot gnu dot org]

------- Comment #2 from pinskia at gcc dot gnu dot org  2009-01-22 01:30 -------
Confirmed, more reduced testcase:
typedef int __m64 __attribute__ ((__vector_size__ (8)));
__inline __m64 _m_pshufw (){}
typedef unsigned char uint8;
void dummy (
            const int input_bpl,
            const unsigned char * input
            , unsigned char * output
            , unsigned long x1) {
  uint8 *pix_end_ptr = output + x1*4;
  __m64 m_original ;
  __m64 m_base_addr = __builtin_ia32_vec_init_v2si (0, input_bpl);
  __m64 m_addr =  __builtin_ia32_paddd (m_original, m_base_addr);
  __m64 *a0 = ( __m64 *)(input);
  for (; output < pix_end_ptr; output += 4)
  {
    a0 = (__m64 *)(input  + __builtin_ia32_vec_ext_v2si (m_addr, 0));
    m_addr = _m_pshufw();
    __builtin_prefetch (a0, 0);
  }
}


-- 

pinskia at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever Confirmed|0                           |1
  GCC build triplet|i686-unknown-linux-gnu      |
   GCC host triplet|i686-unknown-linux-gnu      |
 GCC target triplet|i686-unknown-linux-gnu      |i?86-*-*
   Last reconfirmed|0000-00-00 00:00:00         |2009-01-22 01:30:40
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38931