[Bug tree-optimization/38401] TreeSSA-PRE load after store missed optimization

[amylaar at gcc dot gnu dot org]

------- Comment #20 from amylaar at gcc dot gnu dot org  2009-01-13 14:00 -------
(In reply to comment #19)
> Joern, nobody is forcing you to follow the crowd if you think the crowd is
> going in the wrong direction.

I have evidence that the direction is wrong.  I added a new option to disable
partial-partial pre while keeping the rest of -O3 and -ftree-pre enabled.
This got EEMBC bitmnp back to the level of 4.2.1 (unmodified 4.4.0 needs 2.55
times the amout of cycles).  fbital00 also improved, although it regained only
a little of the performance that it lost since 4.2.1 - cycle count is now down
6% against unmodified gcc 4.4.0 .  Overall the disabling of partial-partial
is also beneficial for EEMBC; there are a few other benchmarks that improved
5 or 6 percent, and the worst regressions are one and two percent.

These are the changes in the geometric means of cycle counts by disabling
partial-partial redundancy elimination per EEMBC benchmark suite:

automotive: 5.73% improvement
consumer:   0.04% improvement
networking: 0.37% improvement
office:     1.39% worse
telecom:    0.00% worse


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38401