[Bug target/39139] [4.4 Regression] ICE with stringop and register var

[hjl dot tools at gmail dot com]

------- Comment #20 from hjl dot tools at gmail dot com  2009-02-09 21:09 -------
(In reply to comment #19)
> No.  This bug is about all targets, not just x86-64, and is about code which
> follows extend.texi documentation (Extended Asm and Explicit Reg Vars) for
> years (glibc e.g. uses it this way for more than 10 years).  Do you suddenly
> want to rule all that code invalid?
> See glibc INLINE_SYSCALL and INTERNAL_SYSCALL macros on all arches, Linux
> asm*/unistd.h _syscall* macros until very recently, etc.
> 

If you don't get ICE, you don't have to change anything. If
you do get ICE, you may have to update.


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39139