[Bug target/37364] [4.4 Regression] IRA generates inefficient code due to missing regmove pass

[Joey dot ye at intel dot com]

------- Comment #21 from Joey dot ye at intel dot com  2008-10-25 04:14 -------
To me scheduler is irrelevant here. GCC has no core2 pipeline description so
the instruction scheduling doesn't looks optimized. But for OOO processor like
core2, IMHO scheduling shouldn't make that much difference. Also core2 + no-ira
doesn't hurt, which means core2 scheduling is not the root cause.

Instead old code uses different register for loading, but IRA code always uses
xmm7 as load target. Need to figure out two questions:
1. why instructions from core2+ira runs slower than ira?
2. why core2+ira generate so different code as non-core2?

Scheduler dump for core2:
;;      insn  code    bb   dep  prio  cost   reservation
;;      ----  ----    --   ---  ----  ----   -----------
;;      108    47     4     0     0     0   nothing     : 70 109 43
;;       43   102     4     1     0     0   nothing     : 70 51 117 114 67 109
;;      109    47     4     2     0     0   nothing     : 70 44
;;       44   102     4     1     0     0   nothing     : 70 57 55 59 67
;;       45   102     4     0     0     0   nothing     : 70 65 67 112 110
;;       46   102     4     0     0     0   nothing     : 70 55 49 67 61
;;      110   102     4     1     0     0   nothing     : 70 65 61
;;       61   720     4     2     0     0   nothing     : 70 55 62
;;       62   720     4     1     0     0   nothing     : 70 47 111


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37364