mips64vrel-elf code gen bug

[Nick Clifton]

Hi Eric, Hi Richard,

  We have received a bug report against the mips64vrel-elf toolchain
  which is reproducible with the mainline sources.  Since it (appears
  to) involve MIPS code generation and I know almost nothing about
  MIPS I am passing it on to you in the hopes that you might be able
  to fix it, or at least point me in the right direction.

  To reproduce the problem compile the attached two files with:

    % mips64vrel-elf 128201-1.c 128201-2.c -Tddb.ld -mabi=32 -march=vr5000

  Then run it with the simulator:  

    % mips64vrel-elf-run a.out 
    FPR 4 (format single) being accessed with format double - setting to unknown (PC = 0xa0100364)
    -2.333333 (-2.333333)

  Note the error message from the simulator.  The problem appears to
  be $f4 register used by the sub.d instruction.  I suspect, but do not
  know for sure, that this is somehow connected with the store_df_high
  pattern in mips.md.

  Any clues or solutions ?

Cheers
  Nick

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