[Bug rtl-optimization/6585] Redundant store/load instruction pairs on ix86

[bruno at clisp dot org]

------- Additional Comments From bruno at clisp dot org  2005-06-27 11:50 -------
Indeed, the result is much better now, nearly optimal. 
As you say, the only further optimization possible is that a better 
register allocation could get rid of the 
      movl    %edx, %esi 
and 
      movl    %ebx, %edi 
instructions. 
 

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=6585