[Bug rtl-optimization/19680] sub-optimial register allocation with sse

[rth at gcc dot gnu dot org]

------- Additional Comments From rth at gcc dot gnu dot org  2005-01-31 21:12 -------
(In reply to comment #21)
>   4010ce:       0f 29 6c 24 10          movaps %xmm5,0x10(%esp)
>   4010de:       0f 59 5c 24 10          mulps  0x10(%esp),%xmm3
>   4011a1:       0f 29 04 24             movaps %xmm0,(%esp)
>   4011af:       0f 56 0c 24             orps   (%esp),%xmm1

These instruction patterns didn't change.  I only fibbed wrt "int" inputs.

It's not impossible that some of this is due to adding the const to the
builtin signatures, but...

> Just to be sure i've tried that patched version on my app, and it's slower
> than the unpatched version (both with -fno-gcse).

So, overall the combination of the two patches is a lose?  How about each
patch individually?

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19680