[Bug rtl-optimization/19680] sub-optimial register allocation with sse

[rth at gcc dot gnu dot org]

------- Additional Comments From rth at gcc dot gnu dot org  2005-01-30 18:04 -------
Ok, I see what Intel is doing.  It's computing an index by 16 by doing

  addl %ecx,%ecx
  movl (%ebx, %ecx, 8), %eax

instead of

  sall $4, %ecx
  movl (%ebx, %ecx), %eax

which, considering the suckitude of the P4 shifter, is a win.  It should
not be a win for any other cpu.

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19680