[Bug middle-end/19329] [3.4 Regression] Bitfield operations cause shifts with 0-count to slip through backends

cvs-commit at gcc dot gnu dot org gcc-bugzilla@gcc.gnu.org
Wed Jan 26 21:45:00 GMT 2005


------- Additional Comments From cvs-commit at gcc dot gnu dot org  2005-01-26 21:44 -------
Subject: Bug 19329

CVSROOT:	/cvs/gcc
Module name:	gcc
Changes by:	marekm@gcc.gnu.org	2005-01-26 21:44:26

Modified files:
	gcc            : ChangeLog 
	gcc/config/avr : avr.c avr.md 

Log message:
	PR target/19293
	PR target/19329
	* config/avr/avr.c (notice_update_cc): Only set condition code for
	ashrqi3 if shift count > 0.
	(out_shift_with_cnt): Handle shift count <= 0 as a no-op.
	(ashlqi3_out, ashlhi3_out, ashlsi3_out, ashrqi3_out, ashrhi3_out,
	ashrsi3_out, lshrqi3_out, lshrhi3_out, lshrsi3_out): Handle shift
	count <= 0 as a no-op, and shift count >= width by copying zero
	or sign bit to all bits of the result.
	* config/avr/avr.md (all shifts): Add alternatives for zero shift
	count, with attribute "length" set to 0 and "cc" set to "none".

Patches:
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=2.7290&r2=2.7291
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/avr/avr.c.diff?cvsroot=gcc&r1=1.127&r2=1.128
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/avr/avr.md.diff?cvsroot=gcc&r1=1.47&r2=1.48



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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19329



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