[Bug target/25268] ICE on lshrdi3_31 pattern

jakub at gcc dot gnu dot org gcc-bugzilla@gcc.gnu.org
Wed Dec 7 08:18:00 GMT 2005



------- Comment #3 from jakub at gcc dot gnu dot org  2005-12-07 08:18 -------
BTW, is the s390 hw really masking the shift count with 63 for all insns,
or just the DImode shifts and with 31 for SImode shifts?
I'd say targets masking the shift count to number of bits of *shift<mode>3's
mode is very common on many targets, perhaps it would be better not to have
a special case in s390{,x} backend, but instead create a target macro
(or struct gcc_target's bool field) that would say if ASHIFT, LSHIFTRT,
ASHIFTRT,
ROTATE and ROTATERT mask the shift count to the number of bits in the shift
mode
(well, for ROTATE and ROTATERT I think that's true on all targets).
Then if that target macro is true, simplify_rtx could simplify
(*shift*:<mode> (reg:<mode>) (and:<mode2> (reg:<mode2>) (const_int C)))
into
(*shift*:<mode> (reg:<mode>) (reg:<mode2>)) if
(INTVAL (c) & (GET_MODE_BITSIZE (mode) - 1)) == GET_MODE_BITSIZE (mode) - 1)

Any ideas on what targets does say
(set (reg X) (const_int 65))
...
(set (reg:DI Y) (ashift:DI (reg:DI Y) (reg X)))
result in Y << 1 rather than in Y = 0?


-- 

jakub at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rth at gcc dot gnu dot org


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25268



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