[Bug target/15286] ICE cause by reload

[dje at gcc dot gnu dot org]

------- Additional Comments From dje at gcc dot gnu dot org  2004-10-24 02:59 -------
pr15286.c:72: error: unrecognizable insn:
(insn 496 167 381 0 (set (mem:SI (plus:SI (reg/f:SI 1 r1)
                (const_int 204 [0xcc])) [15 clock_start+0 S4 A8])
        (subreg:SI (reg:DI 32 f0) 4)) -1 (nil)
    (nil))

insn 496 is generated by reload, but it is generated for insn 167

(insn:HI 167 427 381 0 (set (subreg:DI (reg/v:SI 279 [ clock_start ]) 0)
        (fix:DI (reg:DF 294))) 239 {fix_truncdfdi2} (insn_list:REG_DEP_TRUE 484
(nil))
    (expr_list:REG_DEAD (reg:DF 294)
        (nil)))

regclass appears to be choosing a correct register class

  Register 279 costs: BASE_REGS:2620000 GENERAL_REGS:2620000 LINK_REGS:2620474
CTR_REGS:2620474 LINK_OR_CTR_REGS:2620474 SPECIAL_REGS:2620474
SPEC_OR_GEN_REGS:2620474 NON_FLOAT_REGS:2620474 MEM:2620948
  Register 279 pref GENERAL_REGS, else NON_FLOAT_REGS
Register 279 used 2 times across 70 insns; set 1 time; user var; crosses 5
calls; 4 bytes; pref GENERAL_REGS, else NON_FLOAT_REGS.

But then reload chooses an FPR.  It places a float value (reg:DF) in a GPR (r0)
and places an integer subreg in a FPR (f0).

Reloads for insn # 167
Reload 0: FLOAT_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
        reload_out_reg: (subreg:DI (reg/v:SI 279 [ clock_start ]) 0)
Reload 1: reload_in (DF) = (reg:DF 0 r0 [294])
        reload_out (DI) = (subreg:DI (reg/v:SI 279 [ clock_start ]) 0)
        FLOAT_REGS, RELOAD_OTHER (opnum = 1)
        reload_in_reg: (reg:DF 0 r0 [294])
        reload_out_reg: (subreg:DI (reg/v:SI 279 [ clock_start ]) 0)
        reload_reg_rtx: (reg:DF 32 f0)


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=15286