[Bug rtl-optimization/6585] Redundant store/load instruction pairs on ix86

[bruno at clisp dot org]

------- Additional Comments From bruno at clisp dot org  2004-10-11 11:55 -------
This result is even better: shorter than the previous ones, and there are 
no useless moves between registers any more. 
 
However, there are more useless moves from register to stack slot and back 
from stack slot to register. They could be eliminated. 
 
Commented listing: 
 
mul: 
        subl    $20, %esp 
        movl    32(%esp), %ecx		b0 
        movl    24(%esp), %eax		a0 
        movl    %ebx, 8(%esp)				; save %ebx 
        movl    36(%esp), %ebx		b1 
        movl    %edi, 12(%esp)				; save %edi 
        movl    24(%esp), %edi		a0 
        movl    %ebp, 16(%esp)				; save %ebp 
        mull    %ecx			%edx:%eax := a0*b0 
        imull   28(%esp), %ecx		a1*b0 
        imull   %ebx, %edi		a0*b1 
        movl    8(%esp), %ebx				; restore %ebx 
        movl    %edx, %ebp		hi 
        movl    %eax, (%esp)				USELESS! 
        addl    %edi, %ebp		hi+a0*b1 
        movl    (%esp), %eax				USELESS! 
        leal    (%ebp,%ecx), %ecx	hi+a0*b1+a1*b0	COULD GO INTO %edx 
DIRECTLY 
        movl    12(%esp), %edi				; restore %edi 
        movl    %ecx, 4(%esp)				USELESS! 
        movl    16(%esp), %ebp				; restore %ebp 
        movl    4(%esp), %edx				USELESS! 
        addl    $20, %esp 
        ret 
 

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=6585