[Bug rtl-optimization/13366] ICE using MMX/SSE builtins with -O
uros at kss-loka dot si
gcc-bugzilla@gcc.gnu.org
Mon Dec 20 15:39:00 GMT 2004
------- Additional Comments From uros at kss-loka dot si 2004-12-20 15:39 -------
Equivalent SSE2 version works OK:
typedef int v8hi __attribute__ ((mode (V8HI)));
int
f (unsigned short n)
{
v8hi vec = { 0, 0, 0, 0, 0, 0, 1, n };
v8hi hw = __builtin_ia32_pmulhw128 (vec, vec);
return (__builtin_ia32_pextrw128 (hw, 0));
}
SSE2 example produces following RTL:
(insn 13 11 15 1 (set (reg/v:V8HI 59 [ vec ])
(const_vector:V8HI [
(const_int 0 [0x0])
(const_int 0 [0x0])
(const_int 0 [0x0])
(const_int 0 [0x0])
(const_int 0 [0x0])
(const_int 0 [0x0])
(const_int 0 [0x0])
(const_int 0 [0x0])
])) -1 (nil)
(nil))
(insn 15 13 16 1 (parallel [
(set (subreg:SI (reg/v:V8HI 59 [ vec ]) 12)
(and:SI (subreg:SI (reg/v:V8HI 59 [ vec ]) 12)
(const_int -65536 [0xffff0000])))
(clobber (reg:CC 17 flags))
]) -1 (nil)
(nil))
...
and MMX version produces:
(insn 13 11 15 1 (clobber (reg/v:V4HI 59 [ vec ])) -1 (nil)
(nil))
(insn 15 13 17 1 (parallel [
(set (subreg:SI (reg/v:V4HI 59 [ vec ]) 0)
(and:SI (subreg:SI (reg/v:V4HI 59 [ vec ]) 0)
(const_int -65536 [0xffff0000])))
(clobber (reg:CC 17 flags))
]) -1 (nil)
(nil))
...
The trouble is in (insn 13). There is no setting of reg 59 to zero.
Also, mainline does not ICE for
v4hi vec = { 0, 0, 0, n };
and its SSE2 equivalent as suggested in comment #6 for both MMX and SSE2 versions.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13366
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