[Bug optimization/12249] New: ARM link register is not saved during 64-bit operation

[Peter_Hornung at siemens dot com]

PLEASE REPLY TO gcc-bugzilla@gcc.gnu.org ONLY, *NOT* gcc-bugs@gcc.gnu.org.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12249

           Summary: ARM link register is not saved during 64-bit operation
           Product: gcc
           Version: 3.3
            Status: UNCONFIRMED
          Severity: critical
          Priority: P2
         Component: optimization
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: Peter_Hornung at siemens dot com
                CC: gcc-bugs at gcc dot gnu dot org
 GCC build triplet: i586-pc-linux-gnu
  GCC host triplet: i586-pc-linux-gnu
GCC target triplet: arm-unknown-elf

this tiny c++ function returns to a invalid address because the register LR is 
not saved before it is reused in the function:

extern "C" unsigned long long xxx;
class CEventBug
{
	public:
	CEventBug ();
	unsigned int wait (unsigned long long endTime);
};

extern "C" unsigned int EventWaitForSignal (void* event, unsigned int 
waitMillisec)
{
	CEventBug*	pEv = static_cast <CEventBug*> (event);
	return pEv->wait (xxx + (waitMillisec / 10));
}

it is being compiled with this command line:
arm-elf-g++ -ansi -fno-rtti -ffor-scope -fno-exceptions -finline -Wall -W  -Wno-
long-long -save-temps -fno-builtin -mcpu=arm7tdmi -mbig-endian  -O3 -g -c -o 
test.o test.cpp

arm-elf-objdump -d test.o results in this:
test.o:     file format elf32-bigarm

Disassembly of section .text:

00000000 <EventWaitForSignal>:
   0:	e52d4004 	str	r4, [sp, -#4]!
   4:	e59f401c 	ldr	r4, [pc, #1c]	; 28 <EventWaitForSignal+0x28>
   8:	e08e2194 	umull	r2, lr, r4, r1
   c:	e59f1018 	ldr	r1, [pc, #18]	; 2c <EventWaitForSignal+0x2c>
  10:	e8910018 	ldmia	r1, {r3, r4}
  14:	e1a011ae 	mov	r1, lr, lsr #3
  18:	e0942001 	adds	r2, r4, r1
  1c:	e2a31000 	adc	r1, r3, #0	; 0x0
  20:	e8bd0010 	ldmia	sp!, {r4}
  24:	eafffffe 	b	24 <EventWaitForSignal+0x24>
  28:	cccccccd 	stcgtl	12, cr12, [r12], #820
  2c:	00000000 	andeq	r0, r0, r0