[Bug target/11259] [avr] gcc Double 'andi' missed optimization

[roger at eyesopen dot com]

------- Additional Comments From roger at eyesopen dot com  2003-11-11 04:23 -------
The AVR backend defines its lshrqi3 patterns as opaque "macro" sequences,
hence the fact that "x >> 4" is implemented as a swap/rotate followed by
an and instruction is never exposed to GCC's RTL optimizers.  If it were,
the two ands would be optimized away by CSE, combine or peephole, as they
are for other targets.

As there's nothing the middle-end can do unless the AVR backend is rewritten
to use RTL expanders, I'm changing this PR's component to target/11259.


-- 
           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|optimization                |target


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11259