[Bug optimization/10904] [Sparc64] invalid (misaligned) FP register

[ebotcazou@gcc.gnu.org]

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10904


ebotcazou@gcc.gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
           Priority|P1                          |P3
            Summary|[3.3/3.4 regression] [Sparc]|[Sparc64] invalid
                   |invalid (misaligned) FP     |(misaligned) FP register
                   |register                    |


------- Additional Comments From ebotcazou@gcc.gnu.org  2003-05-22 10:12 -------
Um, no, this is actually a progression: the code emitted by GCC 3.2.1, 3.2.2 and
3.2.3 is wrong:

	fdtox	%f4, %f2
	st	%f2, [%fp+2027]
	ld	[%fp+2027], %o0
	sra	%o0, 0, %l1

We should have

	st	%f3, [%fp+2027]

because of the big-endianness of Sparc CPUs.


With 3.3 we have:

	fdtox	%f10, %f7
	st	%f8, [%fp+2027]
	ld	[%fp+2027], %g1
	sra	%g1, 0, %l1

That's slighty better because we correctly take the lower SI part of a DI value.
But:

	fdtox	%f10, %f7

is illegal because %f7 in an odd FP register.




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